Logic Circuits Research Articles

Implication Logic Circuit Based on a Graphene Oxide Complementary Resistive Switching Device

AbstractThe logic circuit is the main component of an integrated circuit chip that dictates the operation and performance of the chip. The logic circuit based on a memristor can improve the integration and operation speed of the existing integrated circuit and reduce the chip size and the number of devices used by a single logic circuit. However, most of the research on logic circuits based on memristors has focused only on simulations, and research on the realization of logic circuits by hardware using actual memristors is limited. In this paper, a memristor based on graphene oxide with stable complementary resistive switching characteristics is fabricated, a logic circuit is built by using this device, and the logic functions of “IMP,” “AND,” and “NOR” are successfully realized. The complementary resistive switching device can alleviate the severe power loss caused by the memory separation of the von Neumann architecture. Moreover, its unique structure enables it to realize material logic independently without the use of multiple memristors and resistors, providing a new scheme for the physical realization of logic circuits. It also opens up a new path for integrated chips to break through von Neumann architecture.

Conversion between digital and analog resistive switching behaviors and logic display application of photoresponsive ZnO nanorods-based memristor

Memristors have shown great application prospects in next-generation non-volatile memory (NVMs) and brain-inspired computing systems, but various application prospects have different requirements for device performance. Currently, it is difficult to precisely regulate the conversion of memristive effects between analog and digital due to the complex resistive switching mechanism. In this work, size-controlled ZnO nanorods was achieved by adjusting the concentration of the surfactant polyethyleneimine (PEI), and further research was conducted for the memristive effect of the as-prepared memristors based on ZnO nanorods with different sizes. The results showed that PEI accelerates the protonation process, leading to the increase of OH– ions, which further leads to the transition of the memristive effect of the as-prepared device from digital to analog as the PEI concentration increases. Moreover, the optical controlled logic display function was achieved in the memristor based on the light-sensitive properties of the ZnO nanorods. Therefore, this work lays the foundation that the memristor with analog and digital memristive effect can control and enrich the application prospects of memristor.

Laponite-activated AIE supramolecular assembly with modulating multicolor luminescence for logic digital encryption and perfluorinated pollutant detection

Recently, the non-covalently activated supramolecular scaffold method has become a prominent research area in the field of intelligent materials. Here, the inorganic clay (LP) promoted the AIE properties of 4,4′,4″,4‴-(ethene-1,1,2,2-tetrayltetrakis(benzene-4,1-diyl))tetrakis(1-ethylpyridin-1-ium) (P-TPE), showing an astonishing 42-fold enhancement of the emission intensity of the yellow-green luminescence and a 34-fold increase of the quantum yield via organic-inorganic supramolecular strategy as well as the efficient light-harvesting properties (energy transfer efficiency up to 33 %) after doping with the dye receptor Rhodamine B. Furthermore, the full-color spectral regulation, including white light, was achieved by adjusting the ratio of the donor to the acceptor component and co-assembling with the carbon dots (CD). Interestingly, this TPE-based non-covalently activated full-color supramolecular light-harvesting system (LHS) could be achieved not only in aqueous media but also in the hydrogel and the solid state. More importantly, this panchromatic tunable supramolecular LHS exhibited the multi-mode and quadruple digital logic encryption property as well as the specific detection ability towards the perfluorobutyric acid and the perfluorobutanesulfonic acid, which are harmful to human health in drinking water. This result develops a simple, convenient and effective approach for the intelligent anti-counterfeiting and the pollutant sensing.

Photoelectrochemical properties of self-powered corundum-structured Ga2O3nanorod array/fluorine-doped SnO2photodetectors modulated by precursor concentrations.

Herein, corundum-structured Ga2O3(α-Ga2O3) nanorod array/fluorine-doped SnO2(FTO) structures have been fabricated by hydrothermal and thermal annealing processes with different precursor concentrations from 0.01 M to 0.06 M. The diameter and length of the nanorod arrays are much larger with increasing precursor concentrations due to more nucleation sites and precursor ions participating in the reaction procedures. The optical bandgap decreases from 4.75 eV to 4.47 eV because of the tensile stress relieving with increasing the precursor concentrations. Based on self-powered photoelectrochemical (PEC) photodetectors, the peak responsivity is improved from ~0.33 mA/W for 0.06 M to ~1.51 mA/W for 0.02 M. Schottky junctions can be formed in PEC cells. More photogenerated carriers can be produced in wider depletion region. From Mott-Schottky plots, the depletion regions become much wider with decreasing the precursor concentrations. Therefore, the enhance responsivity is owing to the wider depletion regions. Due to the reduced possibility of photogenerated holes captured by traps ascribed from fewer green and yellow luminescence defects, smaller charge transfer resistance, and shorter transportation route, the decay time becomes much faster through decreasing the precursor concentrations. Compared with the other self-powered α-Ga2O3-nanorod-array-based PEC photodetectors, it shows the fastest response time (decay time of 0.005 s/0.026 s) simply modulated by precursor concentrations for the first time without employing complex precursors, seed layers or special device designs. Compared with other high-responsivity monoclinic Ga2O3(α-Ga2O3) self-powered photodetectors, our devices also show comparable response speed with simple control and design. This work provides the realization of fast-speed self-powered Ga2O3based solar-blind ultraviolet photodetectors by simple modulation processes and design, which is a significant guidance for their applications in warnings, imaging, computing, communication and logic circuit, in the future.

N-type semiconducting hydrogel.

Hydrogels are an attractive category of biointerfacing materials with adjustable mechanical properties, diverse biochemical functions, and good ionic conductivity. Despite these advantages, their application in electronics has been restricted because of their lack of semiconducting properties, and they have traditionally only served as insulators or conductors. We developed single- and multiple-network hydrogels based on a water-soluble n-type semiconducting polymer, endowing conventional hydrogels with semiconducting capabilities. These hydrogels show good electron mobilities and high on/off ratios, enabling the fabrication of complementary logic circuits and signal amplifiers with low power consumption and high gains. We demonstrate that hydrogel electronics with good bioadhesive and biocompatible interface can sense and amplify electrophysiological signals with enhanced signal-to-noise ratios.

Erasable and Field Programmable DNA Circuits Based on Configurable Logic Blocks.

DNA is commonly employed as a substrate for the building of artificial logic networks due to its excellent biocompatibility and programmability. Till now, DNA logic circuits are rapidly evolving to accomplish advanced operations. Nonetheless, nowadays, most DNA circuits remain to be disposable and lack of field programmability and thereby limits their practicability. Herein, inspired by the Configurable Logic Block (CLB), the CLB-based erasable field-programmable DNA circuit that uses clip strands as its operation-controlling signals is presented. It enables users to realize diverse functions with limited hardware. CLB-based basic logic gates (OR and AND) are first constructed and demonstrated their erasability and field programmability. Furthermore, by adding the appropriate operation-controlling strands, multiple rounds of programming are achieved among five different logic operations on a two-layer circuit. Subsequently, a circuit is successfully built to implement two fundamental binary calculators: half-adder and half-subtractor, proving that the design can imitate silicon-based binary circuits. Finally, a comprehensive CLB-based circuit is built that enables multiple rounds of switch among seven different logic operations including half-adding and half-subtracting. Overall, the CLB-based erasable field-programmable circuit immensely enhances their practicability. It is believed that design can be widely used in DNA logic networks due to its efficiency and convenience.

Transfer-free robust n-type graphene field-effect transistors for digital logic electronic devices

Graphene has been hailed as wonder materials for electronics due to its outstanding charge transport properties. However, its lack of an electronic bandgap has hindered its application to large-scale field-effect transistor (FET) circuits, thereby making bandgap opening a key priority. Further, the fabrication of graphene devices to date conventionally requires the transfer of graphene from its growth substrate to a target substrate, which introduces defects and deteriorates the device performance. To overcome these challenges, we demonstrate a transfer-free approach for the low-temperature growth (∼100 °C) onto TiO2–x (∼10 nm) buffer layer and in-situ nitrogen doping of monolayer graphene, which enables stretchable nitrogen-doped graphene-based FETs with cutting-edge performance and stability. Hybridizing a TiO2–x channel with the nitrogen-doped graphene, nitrogen-doped graphene-based FETs could be achieved with an on-off ratio of ∼2 × 108 and an electron mobility of ∼1,500 cm2V–1s–1 for mainstream digital logic devices. Such devices exhibit high reproducibility and wafer-scale uniformity, thermal, bias-stress, long-term stability, and robust flexibility and stretchability. The scalability and versatility of this transfer-free approach for the flexible and stretchable FETs pave the way for high-performance nitrogen-doped graphene-based digital logic circuits.

NBTI Effect Survey for Low Power Systems in Ultra-Nanoregime

Background: Electronic device scaling with the advancement of technology nodes maintains the performance of the logic circuits with area benefit. Metal oxide semiconductor (MOS) devices are the fundamental blocks for building logic circuits. Area minimization with higher efficiency of the circuits motivates the researchers of very large-scale integration (VLSI) design. Moreover, the reliability of digital circuits is one of the biggest challenges in VLSI technology. A major issue in reliability is negative bias temperature instability (NBTI) degradation. NBTI affects the efficiency and reliability of electronic devices Methods: This paper presents a review of NBTI physical-based mechanisms. NBTI's impact on VLSI circuits and techniques has been studied to mitigate and compensate for the effect of NBTI. Results: This review paper presents an idea to relate the NBTI and leakage mitigation techniques. This study gives an overview of the efficiency, complexity, and overhead of NBTI mitigation techniques and methodologies. Conclusion: This survey provides a brief idea about NBTI degradation by using reliability simulation. Moreover, the extensive aging effect is discussed in the paper.

GaN monolithic digital units on P-GaN platform

Gallium nitride (GaN)-based digital integrated circuits (ICs) are constructed on the commercially available GaN-on-Si wafer designed for pGaN gate HEMT. The functions of inverter, NAND, AND, NOR, and OR logic circuits are successfully realized based on direct-coupled field-effect transistor logic (DCFL) structure. Under a drive voltage of 5V and a load ratio of 20, the low output (VOL) can reach as low as 0.1V. Additionally, a functional-oriented driver, a SR flipflop, and a NOR gate D flipflop are constructed. All the transient tests at a frequency of 100 kHz and temperatures up to 200 °C exhibit satisfying performance characteristics.

Modeling and Simulation of Phase Change Memory Using Digital Logic Implementation Approach

Phase Change Memory (PCM) adapts to space utilization and bit storage for displaying amorphous or crystalline states. This change of state relies on the nature of the information and its non-volatility period. As is well known Digital Logic operations are influential over memory modeling, this article introduces a Propagative Adaptability Decision Module (PADM) using DL. This module is utilized based on the information non-volatility across overflow and underflow memory conditions. This utilization-based classification induces the digital logic influence by swapping the states that are robust for further propagative adaptability. This means the possible logical combinations of 0’s and 1’s are used for deciding the states of PCM. The logical operations using OR and NOT are used for reducing overflows whereas the AND and NOT combinations are used for preventing underflows. This reduces the volatility show-up in two distinct phases of memory utilization. Therefore, the 0 and 1 combinations are validated for all the logical operations to ensure propagative memory swapping for balancing the overflow and underflow conditions. This process does not mark up the highest 1 or 0 combination individually due to state changes. The proposed module is validated using swapping rate, time, complexity, and overflow conditions.

High Mobility Amorphous Polymer‐Based 3D Stacked Pseudo Logic Circuits through Precision Printing

AbstractDirect printing of conjugated polymer thin‐film transistors enables the fabrication of deformable devices with low cost, high throughput, and large area. However, a relatively poor device performance of printed devices remains a major obstacle to their application in high‐end display backplanes and integrated circuits. In this study, high‐performance and highly stackable printed organic transistors is developed, arrays, and circuits using a near‐amorphous polymer, indacenodithiophene‐co‐benzothiadiazole (IDT‐BT). The printed devices exhibited high saturation mobility (>1 cm2 V−1 s−1), high on/off ratio (>107), and low subthreshold slope (245 mV dec−1). In addition, 16 × 16 printed IDT‐BT arrays achieved 100% fabrication yield, with excellent device‐to‐device uniformity and low variations of mobility (9.55%) and threshold voltage (4.51%), and good operational and environmental stability (>365 days). Furthermore, five stacked 3D transistors are demonstrated with an excellent 3D uniformity without compromising device performance due to a low required thermal budget for processing amorphous IDT‐BT. Finally, a new concept of 3D universal logic gate with high voltage gain (33.91 V/V) and record density (100 printed transistors per cm2) is proposed and fabricated, which is relevant for the commercialization of low‐cost printed display backplanes and high‐density integrated circuits based on highly processable polymeric semiconductors.

Braiding Operations for a Topological Josephson Junction Array Using a Bipolar Current Pulse Generator Controlled by SFQ Logic Circuits

Braiding Operations for a Topological Josephson Junction Array Using a Bipolar Current Pulse Generator Controlled by SFQ Logic Circuits

Digital Logic Based on Superconducting Gate-Controlled Transistors

Digital Logic Based on Superconducting Gate-Controlled Transistors

A binary neural computing unit with programmable gate using SFQ and CMOS hybrid circuit

Abstract Superconducting neural networks hold significant potential for future applications such as natural language processing and image recognition. To this end, we propose a binary neural computing unit implemented using a hybrid circuit of cryogenic CMOS and superconducting technologies. It offers two main advantages: firstly, we utilize current-mode computations for neural unit weight calculations, significantly reducing the unit’s footprint and enabling the potential for higher integration in the future. Secondly, all computations are performed in a low-temperature environment, which implies the possibility of on-chip learning in superconducting neural networks and the potential for achieving faster training rates in the future. We fabricated the chip using Nb 1kA/cm^2 process (1KP) technology and experimentally verified the correctness of the circuit logic. The margins for various control parameters of the circuit are approximately around 30%, and the superconducting circuit power consumption is estimated to be around 4 microwatts.

Memory-compatible perpendicular magnetic tunnel junctions under bi-directional strobe write pulses: A method for generating true random number bits at high speed

We propose an operation method of generating true random number bits with a perpendicular magnetic tunnel junction (pMTJ) already in use as a memory element in spin-transfer-torque driven magnetic random access memory technology. This method uses a set of regularly spaced (or intentionally irregularly spaced), minimum width, and bi-directional fast strobe-write pulses, with read operations after each write. The resulting bit-stream’s statistical properties are analyzed, and a few digital logic operation following the read is described that could significantly improve the resulting bit-streams variance and stability, insulating those from the raw variations of pMTJs.

Design and Evaluation of a New Nanoscale and Cost-Efficient Coplanar Digital Parity Generator Based on Quantum Dots

A parity generator as a combinational logic circuit in digital circuits can generate the parity bit in the transmitter. It is very applicable in digital networking and communications. Also, rather than diodes and transistors, quantum dots will be used in the next-generation circuits. Quantum-dot Cellular Automata (QCA) offers a new platform where binary data is represented by polarized cells that are defined by the electron configurations. Therefore, a coplanar 4-bit parity generator is suggested in this work. This new arrangement eliminates complicated crossovers and provides complete access to all input and output pins. An XOR gate is used to implement the suggested architecture. Simulation waveforms and performance data confirm the proposed circuits’ functioning and advantages. The suggested four-bit parity generator uses less overhead than its equivalents. We simulated and tested the suggested circuit with the assistance of the QCADesigner 2.0.3 simulator. The QCADesigner software findings demonstrate that the suggested design is simpler and less expensive than earlier designs. Compared to the present best design, the suggested four-bit parity generator reduces cell number and latency by 55.29% and 40%, respectively.

An Experimental Research of the Algorithm for Extracting of a Boolean Function Subsystems for Joint Multilevel Optimization

The results of an experimental comparison of programs for technologically independent minimization of complexity of multilevel representations of systems of fully defined functions based on the Shannon expansion are described. The main attention is paid to the effectiveness of using, when synthesizing logical circuits, a program that implements an algorithm for solving the problem of extracting from a system of functions such subsystems for which it is advisable to carry out joint minimization of multi-level representations of subsystems in the form of Binary Decision Diagrams, called BDD-representations, and in the form of Boolean net. The complexity of the representation is estimated by the total number of literals of Boolean variables in a set of interrelated logical equations that define a system of Boolean functions. After extracting the subsystems and their joint minimization, the synthesis of logic circuits is carried out in the design library of custom digital CMOS VLSIs, the results are compared in terms of chip area and speed (time delay) on a stream of 39 industrial examples of circuits. It was found that for 20 examples, the subsystem selection algorithm allows one to obtain better solutions than joint or separate minimization of multi-level representations based on Shannon expansion (13 examples). The three best solutions are obtained by applying the well-known Espresso program for minimizing functions in the DNF class, and the three solutions are obtained by the synthesizer using the original (non-optimized) matrix representations of DNF systems of Boolean functions.

Thinning Solution‐proceed 2D Te for p‐ and n‐channel Junction Field Effect Transistor with High Mobility and Ideal Subthreshold Slope

AbstractTwo‐dimensional non‐layered tellurene (Te) can serve as a promising candidate in transistor applications because of its high carrier mobility and air stability. However, it is still quite challenging in aspect of ultra‐thin channel and gate‐control ability in conventional metal‐oxide‐semiconductor field‐effect transistor architecture. This work proposes a facile thinning strategy for solution‐proceed Te flakes and fabricates a junction field‐effect transistor (JFET) architecture, that has well addressed the above‐mentioned two issues. Through a mild oxidative thinning process, the post‐growth Te flakes are thinned from bulk to few‐layer, guaranteeing the highly efficient electrostatic doping as a transistor channel. Then, a four‐terminal JFET‐based on p‐Te and n‐ReS2 is designed, achieving a multifunctional integration of rectification diode, p‐ and n‐channel transistor in one single device. By accessing different contact scheme, the ReS2/Te p‐n diode is explored with a rectification ratio of 103, the p‐channel JFET exhibits a high hole mobility of 317.6 cm2V−1s−1, ideal low subthreshold swing of 84 mV dec−1. While the n‐channel JFET is obtained with electron mobility of 67.6 cm2 V−1s−1 and SS of 229 mV dec−1. Both p‐ and n‐channel devices showcase clear saturation characteristic with ultra‐small pinch‐off voltage (≈0.4 V), which is crucial for low‐power logical and integrated circuit applications.

Coumarin derivative-functionalized nanoporous silica as an on–off fluorescent sensor for detecting Fe3+ and Hg2+ ions: a circuit logic gate

A highly efficient fluorescent sensor (S-DAC) was easily created by functionalizing the SBA-15 surface with N-(2-Aminoethyl)-3-Aminopropyltrimethoxysilane followed by the covalent attachment of 7-diethylamino 3-acetyl coumarin (DAC). This chemosensor (S-DAC) demonstrates selective and sensitive recognition of Fe3+ and Hg2+ in water-based solutions, with detection limits of 0.28 × 10–9 M and 0.2 × 10–9 M for Hg2+ and Fe3+, respectively. The sensor’s fluorescence characteristics were examined in the presence of various metal ions, revealing a decrease in fluorescence intensity upon adding Fe3+ or Hg2+ ions at an emission wavelength of 400 nm. This sensor was also able to detect ferric and mercury ions in spinach and tuna fish. The quenching mechanism of S-DAC was investigated using UV–vis spectroscopy, which confirmed a static-type mechanism for fluorescence quenching. Moreovre, the decrease in fluorescence intensity caused by mercury and ferric ions can be reversed using trisodium citrate dihydrate and EDTA as masking agents, respectively. As a result, a circuit logic gate was designed using Hg2+, Fe3+, trisodium citrate dihydrate, and EDTA as inputs and the quenched fluorescence emission as the output.Graphic abstract

Nonvolatile Reconfigurable Logic Device Based on Photoinduced Interfacial Charge Trapping in van der Waals Gap.

Due to the increasing complexity in miniaturization of electronic devices, reconfigurable field-effect transistors (RFETs) have emerged as a solution. Although the foundational concepts of RFETs have matured over two decades, ongoing breakthroughs are needed to address challenges such as improving the device performance as well as achieving balanced symmetry between n-type and p-type transport modes with long-term stability. Herein, we present a nonvolatile WSe2-based RFET that utilizes photoassisted interfacial charge trapping at the h-BN and SiO2 interface. Unlike typical RFETs with two gate electrodes, our RFETs achieved polarity control with a single operating gate activated exclusively under white-light exposure. The threshold voltage was tunable, ranging from 27.4 (-31.6 V) to 0.9 (+19.5 V), allowing selective activation of n-type (p-type) operation at VGS = 0 V. Additionally, our WSe2-based RFETs show superior repeatability and long-term stability. Leveraging these advantages, various reconfigurable logic circuits were successfully demonstrated, including complementary inverters and switch circuits as well as pull-up and pull-down circuits, highlighting the potential of WSe2 FETs for future advancements of integrated circuits.